1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing thereof.
2. Related Art
In semiconductor devices of recent years, a delay in signal propagation through an interconnect restricts an operating speed of electronic elements. A delay constant in signal propagation through an interconnect is represented by a product of an interconnect resistance and an interconnect capacitance. Therefore, in order to achieve faster operation of elements, a low dielectric constant material having lower dielectric constant than a conventional silicon dioxide film (SiO2) is employed for an interlayer insulating film, and copper (Cu) having lower electrical resistivity is employed for an interconnect.
A multiple-layered interconnect employing copper as an interconnect material is formed by a damascene process. In typical damascene process, a concave portion such as an interconnect trench or a via hole is formed in an interlayer insulating film, and then a barrier metal film is deposited in the concave portion, and the concave portion is further plugged with a copper film, and thereafter, portions of the copper film and the barrier metal film deposited outside of the concave portion are removed by a chemical mechanical polishing (CMP) process to obtain a copper interconnect or a copper via. The copper film is formed by, first of all, forming a copper thin film serving as a seed layer in the concave portion, and then filling the concave portion with the copper film utilizing the copper thin film as a cathode electrode for an electrolytic plating process.
Technologies for providing an improved electromigration resistance of the copper film are disclosed in Japanese Laid-open patent publication No. 2004-158,897, Japanese Laid-open patent publication No. H11-45,887 (1999) and Japanese Laid-open patent publication No. 2000-174,025. Japanese Laid-open patent publication No. 2004-158,897 discloses a method for forming an electric conductor by ion-implanting an impurity such as carbon (C) and the like into a seed layer of copper, and then performing an electrolytic plating process for copper. It is described that such procedure-provides an improved electromigration resistance of an electric conductor composed of copper.
Japanese Laid-open patent publication No. H11-45,887 discloses a procedure by providing a copper coupling structure that employs a layer containing a copper and another metal material as a seed layer.
Japanese Laid-open patent publication No. 2000-174,025 discloses a configuration having an impurity film containing carbon or the like between copper films. The impurity film is formed by maintaining a status of a substrate being immersed into a plating solution.
Japanese Laid-open patent publication No. 2005-256,178, Japanese Laid-open patent publication No. 2003-142,426 and Japanese Laid-open patent publication No. 2003-129,285 disclose methods that involve performing an electroplating process utilizing a relatively lower current density in initial stage, and then performing an electroplating process utilizing a relatively higher current density, when trenches are filled with a plated copper. It is described that such procedure provides a prevention from generating voids.
Japanese Laid-open patent publication No. 2003-328,180 discloses a configuration employing a plating solution that contains an inhibitor containing polyethylene glycol having molecular weight of 2,000 to 40,000. It is described that such configuration provides a prevention from generating voids even if the via hole has higher aspect ratio.
Meanwhile, C. H. Shih et al, entitled “Design of ECP additive for 65 nm-node technology Cu BEOL reliability”, Proceedings of the IEEE 2005 International Interconnect Technology Conference (IEEE Cat. No. 05TH8780), IEEE, Piscataway, N.J., USA, 6-8 Jun. 2005, pp. 102-104, discloses that impurity in copper film formed by a plating process affects electromigration (EM) and stress induced void (SIV) formation. According to C. H. Shih et al, a presence of impurity in a grain boundary of a copper film provides an improved SIV resistance, while an additive employed for forming impurity of copper provides a deteriorated EM resistance. As described above, an improvement in SIV resistance and an improvement in EM resistance is a trade off, and thus simultaneous enhancements of both resistances can not be achieved in conventional technologies. In the configurations described in above-described conventional technologies, simultaneous improvements in both SIV resistance and EM resistance can not be achieved.